According to a September 7 report from Reuters, ASML plans to work with major chipmakers to adapt its High-NA EUV lithography tools for the large data-centre processors being designed by Nvidia and others.
High-NA EUV tools currently have a smaller mask exposure field than ASML’s established EUV machines.
AI systems require substantially more silicon. In an ASML presentation in January, the Dutch equipment maker said Nvidia’s 2024 Blackwell system requires 2.5 wafers, while a 2027 Rubin Ultra system requires 10 wafers.
High-NA EUV’s half-size exposure field
High-NA EUV is ASML’s next-generation extreme ultraviolet lithography platform. The company’s TWINSCAN EXE:5000 uses a 0.55 numerical aperture and is designed for 8-nanometre resolution.
The EXE:5000 has an exposure field half the size of conventional NXE systems, whose numerical aperture is 0.33. Its anamorphic optics enable finer resolution, but the smaller field creates a manufacturing challenge for very large AI dies.
ASML plans to work with major chipmakers on adapting High-NA EUV tools for large data-centre processors designed by Nvidia and other companies. Reuters described that effort as addressing the tools’ current smaller-mask limitation.
The stated objective does not mean the field-size constraint has already been eliminated.
Nvidia’s Rubin Ultra roadmap
ASML’s own figures illustrate why the issue is becoming more prominent. Its January presentation put the silicon requirement for the 2024 Blackwell system at 2.5 wafers and the projected requirement for the 2027 Rubin Ultra system at 10 wafers.
The silicon requirement rises fourfold over three years in that comparison. Because the presentation frames the figures at the system level, they indicate the scale of manufacturing demand ASML expects from upcoming Nvidia hardware, not the requirement for a single processor die.
For ASML, larger processor designs and rising system-level silicon requirements make the usable exposure field a more consequential part of High-NA deployment. The company’s adaptation programme is aimed at reconciling that field-size constraint with chips at the upper end of data-centre computing.
Intel 18A tests High-NA readiness
The large-chip adaptation work arrives as High-NA EUV moves from development toward manufacturing use. On July 15, ASML said Intel had entered high-volume manufacturing for selected Intel 18A layers using High-NA EUV.
ASML added that Intel’s Panther Lake processors were shipping at yields matched to the existing NXE platform, a milestone limited to selected 18A layers but providing a production reference point for a technology whose broader customer insertion is still being phased in.
At the January press conference, ASML said it had shipped eight High-NA systems and that six were operating. It said it remained on track to meet high-volume manufacturing requirements by the end of 2026, while expecting customer insertion in 2027 and 2028.
Those timelines place Intel’s reported 18A use ahead of the wider insertion period cited by ASML. The next test for the platform will be whether the work on larger exposure requirements can allow High-NA tools to serve the biggest AI processors as adoption expands.
Disclaimer: This article is provided for informational purposes only. It is not offered or intended to be used as legal, tax, investment, financial, or other advice.
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